In recent years, a semiconductor processing device that includes a processor (CPU) is widely used. For example, in an automobile, about 100 semiconductor processing devices are mounted. As such a semiconductor processing device for a specific application, a general-purpose semiconductor processing device is used from the viewpoint of cost. In the actual use of the semiconductor processing device, specialized processing in a specific application is repeatedly performed in many cases and specific instructions are frequently performed. Therefore, a semiconductor processing device that includes a processor to which application-specific instructions are added for each application is used in order to quickly respond to a request to optimize a user application. In such a processor, a method is generally used, in which a dedicated interface is provided for additional instructions and dedicated opcodes are allocated.
FIG. 1A is a diagram illustrating a hardware configuration of a computer that includes a processor to which specific instructions are added. Such a computer is realized as a semiconductor processing device and the semiconductor processing device is included in each part. In FIG. 1A, thick arrow lines indicate the flow of data, thin arrow lines indicate the flow of instructions, and broken arrow lines indicate the flow of an instruction operation control signals.
As illustrated in FIG. 1A, a computer has a processor 11, an instruction memory 21, a data memory 22, and a specific processing arithmetic unit 23 that processes additional instructions. The processor 11 has an instruction decode part 12, an arithmetic unit 13, a register file 14, and a data transfer block 15. The instruction decode part 12 fetches instructions read from the instruction memory 21, generates instruction operation control signals (operation codes: opcodes) for execution in the arithmetic unit 13 by decoding the fetched instructions, and outputs the opcodes to the arithmetic unit 13. Further, the instruction decode part 12 sends information of data for executing the instructions to the data transfer block 15. The data transfer block 15 reads data for executing the instructions from the data memory 22 and stores the data in the register file 14. The arithmetic unit 13 processes the data stored in the register file 14 in accordance with the opcodes (there is a case where data is not used) and stores data of the processing results in the register file 14. The data transfer block 15 reads the data of the processing result from the register file 14 and stores the data in the data memory 22. The above is the general operation of the processor.
When the specific processing arithmetic unit 23 processes additional instructions, the specific processing arithmetic unit 23 is connected to the processor 11. The processor 11 has an interface to connect the specific processing arithmetic unit 23. The interface outputs instruction operation control signals (opcodes) to the specific processing arithmetic unit 23 when the instructions decoded by the instruction decode unit 12 are additional instructions and data are input and output between the specific processing arithmetic unit 23 and the register file 14. The portion having the interface and the arithmetic unit 13 is referred to as an arithmetic part. The specific processing arithmetic unit 23 processes the data stored in the register file 14 in accordance with the opcodes corresponding to the additional instructions and stores data of the processing results in the register file 14.
FIG. 1B is a diagram illustrating an example of an instruction code map possessed by the instruction decode part 12. The instruction decode part 12 has an instruction code map that stores opcodes in correspondence to instructions and reads and outputs the opcodes corresponding to the input instructions.
FIG. 1B illustrates a 4×8 instruction code map and opcodes are generated for 32 instructions. For example, additional instructions are allocated to 1×8 regions in the fourth row and general instructions executed by the arithmetic unit 13 are allocated to 3×8 regions in the first to third rows.
As illustrated in FIG. 1B, of 32 instruction regions, eight instruction regions are allocated to additional instructions. Therefore, general instructions are limited to 24 and additional instructions are limited to eight. Accordingly, it is difficult to sufficiently define the numbers of the executable general instructions and the executable additional instructions. The small number of instructions causes problems not only when the specific processing arithmetic unit 23 that processes additional instructions is connected to execute the additional instructions but also when the arithmetic unit 13 executes special instructions in addition to basic instructions.
If the instruction code map is extended, the number of executable instructions is increased. However, this requires an increase in the number of bits representing the instruction codes, and therefore, the circuit scale of the processor is increased considerably.